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Introduction to performance optimization using Intel SW tools - тест 1

Упражнение 1:
Номер 1
 The Control Unit functions are

Ответ:

 (1) instruction decoding 

 (2) ALU operating 

 (3) data transfer 

 (4) instruction execute 

 (5) ALU startup 


Номер 2
What is the goals of ALU

Ответ:

 (1) instruction decoding 

 (2) drive itself 

 (3) data transfer 

 (4) ariphmetical operations 

 (5) device interconnection 


Номер 3
 Registers are

Ответ:

 (1) memory of ALU 

 (2) memory of CPU 

 (3) interface data memory 


Упражнение 2:
Номер 1
 System bus used for

Ответ:

 (1) data transfer 

 (2) CPU parts interconnection 

 (3) command execution 

 (4) data storage 


Номер 2
 What is CPU speed?

Ответ:

 (1) number of data transfers 

 (2) average command execution time 

 (3) bus data transfer speed 

 (4) number of tasks, executed concurrently 


Номер 3
 x86 speed factors are

Ответ:

 (1) CPU timer speed 

 (2) memory size and the speed of external memory access 

 (3) instruction set and instruction execution speed 

 (4) efficiency of the internal memory and register usage 

 (5) pipeline quality 

 (6) branch prediction quality 

 (7) hardware prefetch quality 

 (8) vector instruction quality 

 (9) parallelization and multi-core technology 


Упражнение 3:
Номер 1
 CPU timer speed is

Ответ:

 (1) frequency of the timer which provides the synchronization inside the processor 

 (2) value of the processor clock frequency 

 (3) speed of the most shorten command 

 (4) minimal quant of the equations 

 (5) sychro-impulse frequency, send by timer 


Номер 2
 Choose the correct statement

Ответ:

 (1) hardware prefetch mechanism tries to guess a memory access plan to load the data before it will be actually accessed 

 (2) caching technique uses spatial locality principle 

 (3) cache aliasing occurs when the data placement is good and registers are loaded without any instructions 


Номер 3
 Memory, which is directly accessed by processor is

Ответ:

 (1) Random Access Memory 

 (2) system register 

 (3) system bus 


Упражнение 4:
Номер 1
What of the following will not cause any change in processor performance?

Ответ:

 (1) CPU clock 

 (2) branch prediction quality 

 (3) operation system 


Номер 2
 Modern Intel processors are

Ответ:

 (1) CISC 

 (2) RISC 

 (3) hybrid of CISC and RISC 


Номер 3
 Why register access latency is lower than RAM?

Ответ:

 (1) registers are placed inside CPU 

 (2) registers are placed inside the very fast cache memory 

 (3) they are accessed parallel with equations 


Упражнение 5:
Номер 1
 Superscalar is

Ответ:

 (1) processor, specialized for scalar operations 

 (2) processor that execute more than one operation at a tick 

 (3) none of the answers 


Номер 2
 Choose the wrong statement

Ответ:

 (1) compiler is a part of microprocessor providing program translation to native code or assembler 

 (2) compiler translates source code to assembler or native code  

 (3) only compiler could open to the high level developer new processor abilities such as additional registers or new commands 


Номер 3
 Superscalarity is

Ответ:

 (1) Ability to operate with vectors 

 (2) Ability to process more than one operation at a tick 

 (3) none of the answers 


Упражнение 6:
Номер 1
 What is used to send data between the processor and the memory or between 
	the processor and the devices?

Ответ:

 (1) system registers 

 (2) ALU 

 (3) system bus 

 (4) RAM 


Номер 2
 Time latency (for RAM) is

Ответ:

 (1) frequency of synchronizing impulses 

 (2) number of ticks required to get one unit of data from memory 

 (3) number of data units are allowed to send the processor at a tick 

 (4) number of operations the processor is able to perform at a tick 


Номер 3
 Superscalarity is

Ответ:

 (1) ability to perform multiple operations at a tick 

 (2) frequency of synchronizing impulses of the microchip 

 (3) number of ticks are required to read one unit from memory 

 (4) maximum number of data elements could be send to the processor at a time 


Упражнение 7:
Номер 1
 The ability to perform multiple operations at a tick is

Ответ:

 (1) vectorization 

 (2) hardware prefetch 

 (3) superscalarity 

 (4) pipeline 

 (5) hyperthreading 


Номер 2
 Bandwidth is

Ответ:

 (1) maximum number of units that could be send to the processor at a time 

 (2) maximum number of operations that the processor can perform at a time 

 (3) maximum number of commands that could be loaded to the pipeline at a time 


Номер 3
 Superscalar is

Ответ:

 (1) multicore 

 (2) processor with multiple execution units 

 (3) processor with "out of order execution" feature 


Упражнение 8:
Номер 1
 Hardware prefetching used for

Ответ:

 (1) parallel calculations 

 (2) predict the address of required data and load it into the cache 

 (3) increase bandwidth of the processor 


Номер 2
 Pipeline is 

Ответ:

 (1) technique that increases a number of processed instructions at a time 

 (2) method predicting the next required data address 

 (3) mechanism to avoid the processor idle 


Номер 3
 In a fully-associative memory

Ответ:

 (1) each block is translated to any part of the cache 

 (2) each block has its own place inside the cache 

 (3) line of the corresponding cache is calculated from the lower part of the address and the exact place in the line is chosen associatively 


Упражнение 9:
Номер 1
In out-of-order execution instructions scheduled according

Ответ:

 (1) to their order in pipeline 

 (2) to the evaluation of their operands 

 (3) to the branch prediction 


Номер 3
Vectorization is parallelization technique when

Ответ:

 (1) the processor applies one operation to multiple data 

 (2) the processor applies different operations in parallel 

 (3) the processor applies one operation to multiple data sequentially 


Номер 4
Cache levels differ by

Ответ:

 (1) the speed of access 

 (2) fist level for scalar, second for superscalar and the third is for vectors 

 (3) by dimensions: one, three and four dimensional cache 

 (4) they are almost equal and not differ 


Упражнение 10:
Номер 1
Number of ticks, required to transfer one unit from the memory is

Ответ:

 (1) latency 

 (2) system clock 

 (3) bandwidth 


Номер 2
Number of units could be sent to the processor at once is

Ответ:

 (1) latency 

 (2) memory amount and external memory rate 

 (3) bandwidth 


Номер 3
Type of cache, where any memory block could be loaded into any part of the cache

Ответ:

 (1) direct mapping memory 

 (2) fully-associative cache 

 (3) reverse mapping memory 




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