Главная / Программирование / Introduction to performance optimization using Intel SW tools / Тест 5

Introduction to performance optimization using Intel SW tools - тест 5

Упражнение 1:

Номер 1

Loop vectorization is

Ответ:

(1) change scalar operations to vector

(2) raster to vector image conversion

(3) internal processor function

(4) compiler optimization

Номер 2

MMX technology provides:

Ответ:

(1) a set of instructions to operate packed integer data types

(2) program package for multimedia

(3) additional registers

(4) fast floating point operation set

(5) additional processor module for audio and video conversion

Номер 3

SSE is:

Ответ:

(1) technology applies single instruction to multiple data

(2) technology to execute code at server side

(3) streaming SIMD processor extension

(4) server configuration extension

(5) programming language

Упражнение 2:

Номер 1

SIMD is:

Ответ:

(1) computation principle provides data parallelism

(2) instruction system for multiuser access

(3) "simple data multiple instructions"

(4) a type of computer memory

(5) "Single instruction multiple data"

Номер 2

Which of the following command line options
	will build a binary for any processor?

Ответ:

(1) -QxSSE4_1

(2) -arch:SSE3

(3) -QaxSSE3_1

(4) -QxSSE3

(5) -arch:SSE2_2

(6) -QaxSSE4_2

(7) -QxSSE2

Номер 3

What is condition for vectorization?

Ответ:

(1) loop dependency absence

(2) usage of special data types

(3) usage of <vector> module

(4) dependent instruction order after optimization kept the same

Упражнение 3:

Номер 1

What is vector instruction for the compiler?

Ответ:

(1) adding vectors

(2) vector multiply by matrix

(3) vector folding

(4) vector substraction

(5) vector power

Номер 2

What of the following is required to execute vector operation?

Ответ:

(1) vectors should form the complete basis in n-dimensional space

(2) vector collinearity absence

(3) vector normalizing

(4) at least one vector module is not zero

(5) none of the answers

Номер 3

May four different variables became components of the same
	vector after the vectorization?

Ответ:

(1) never

(2) may

(3) only if they could be arranged lexigraphically

(4) only for add operation

(5) only for multiply operation

Упражнение 4:

Номер 1

What size do xmm registers have?

Ответ:

(1) 16 bit

(2) 32 bit

(3) 64 bit

(4) 128 bit

(5) 256 bit

Номер 2

What size do ymm registers have?

Ответ:

(1) 16 bit

(2) 32 bit

(3) 64 bit

(4) 128 bit

(5) 256 bit

Номер 3

How many xmm registers does emm64t support?

Ответ:

(1) 4

(2) 8

(3) 16

(4) 32

(5) 64

Упражнение 5:

Номер 1

What is packed data type?

Ответ:

(1) data type without zero bits

(2) data packed by Huffman

(3) a special type used for archivation

(4) vector component data type

(5) scalar forming data type

Номер 2

What is happened to zero bits in packed data type?

Ответ:

(1) nothing

(2) meaningless zero bits are omited

(3) packed by Huffman

(4) vectorized

(5) scalarized

Номер 3

Packed data type operations are

Ответ:

(1) pack and unpack operations only

(2) operations that could be removed from code

(3) vector operations

(4) operations with omiting zero bits

(5) they are abstract for assembler doesn't have any

Упражнение 6:

Номер 1

What is /Qvec-report used for?

Ответ:

(1) to drive vectorization during the compilation

(2) to report vectorization at the execution time

(3) to report vectorization at the compile time

(4) do drive vectorization heuristics

Номер 2

What is  __alignof__  used for?

Ответ:

(1) to align source text

(2) to tell compiler how to align objects

(3) to get the infromation on data type alignment

(4) to get the information on alignment of the variables

Номер 3

Why it is recommended to arrange fields in structure 
	by decrease of their size?

Ответ:

(1) to improve performance

(2) to beautify

(3) to decrease structure size after the alignment

Номер 4

Vectorization is

Ответ:

(1) collecting a program characteristics such as procedure execution time, branch mispredition rate, cache splitting etc.

(2) program source translation to assembler or native code

(3) process of converting from scalar representation where each operation using scalars to vector representation where one operation could use a vector operands

Главная / Программирование / Introduction to performance optimization using Intel SW tools / Тест 5